A sixth-order triple-loop sigma-delta CMOS ADC with 90 dB SNR and 100 kHz bandwidth

The conversion rate of high-resolution wideband sigma-delta ADCs is limited by need for high oversampling ratio, typically 64 or more, for rejection of quantization noise. These rates lead to high amplifier power, large power-hungry digital filters, and difficult-to-drive signal and reference inputs. For 16b performance with low oversampling ratio it is necessary to use high-order noise shaping and/or multi-level quantizers and DACs, both leading to problems in design or manufacture if realized directly. The ADC described here consists of three cascaded second-order three-level loops giving a sixth-order noise-shaping function without linearity and stability problems from component mismatch or quantizer overload.<<ETX>>