Impact of temperature on negative capacitance field-effect transistor

A negative capacitance field-effect transistor (FET) with sub-60 mV/decade subthreshold slope (SS) at different temperatures (i.e. 14.8 mV/decade at 300 K, 15.7 mV/decade at 360 K and 24.3 mV/decade at 400 K) is experimentally demonstrated. A detailed account of the fabrication process of a negative capacitor is first introduced, followed by the measurement setup for the negative capacitance FET. The impact of temperature on negative capacitance FETs is investigated: (i) the equation for the internal voltage gain in the FET as a function of temperature is derived using Gibbs free energy and (ii) internal voltage against gate voltage (V Int against V G), internal voltage gain against gate voltage (dV Int/dV G against V G) and drain current against gate voltage (I D against V G) curves at different temperatures are measured. It is confirmed that internal voltage amplification can be achieved using the ferroelectric capacitor. However, the magnitude of the step-up voltage transformation is reduced, i.e. from 9.5 at 300 K to 2.6 at 400 K. Additionally, the SS is slightly increased (i.e. degrading from 14.8 mV/decade at 300 K to 24.3 mV/decade at 400 K) with increasing temperature; however, all SS values are better than the physical limits of SS as dictated by Boltzmann statistics.