A predictive and parametrized architecture for image analysis algorithm implementations on FPGA adapted to multispectral imaging

The presented parameterised and predictive architecture is dedicated for image analysis algorithms implementations on FPGAs. Image analysis algorithms have shared characteristics. These characteristics serve as a basis for the presented parameterised architecture. The architecture design is based on the linear effort property and reusable IP. For a new algorithm implementation, adaptations only concern a small part of the entire architecture. New IPs are developed in handel-C using the DK design suite tool provided by Celoxica. The design space exploration (DSE) is made off-line with the use of prediction models which results in a shorter design time and the generated architecture will satisfy the given constraints. An example of the design process is presented with the multispectral imaging implementation instead of the particle image velocimetry (PIV) algorithm.

[1]  Wolfgang Fichtner,et al.  Practical design of globally-asynchronous locally-synchronous systems , 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).

[2]  Nathalie Bochard,et al.  A Predictive NoC Architecture for Vision Systems Dedicated to Image Analysis , 2007, EURASIP J. Embed. Syst..

[3]  Pierre Bricaud,et al.  Reuse methodology manual for system-on-chip designs , 1998 .

[4]  Romain Lemaire,et al.  Proposition of a benchmark for evaluation of cores mapping onto NoC architectures , 2005, ReCoSoC.

[5]  Alain Trémeau,et al.  Spectral Sensitivity Estimation for Color Camera Calibration , 2006, CGIV.

[6]  Camel Tanougast,et al.  CuNoC: A Scalable Dynamic NoC for Dynamically Reconfigurable FPGAs , 2007, 2007 International Conference on Field Programmable Logic and Applications.

[7]  R. Adrian Particle-Imaging Techniques for Experimental Fluid Mechanics , 1991 .

[8]  Martti Forsell,et al.  A Scalable High-Performance Computing Solution for Networks on Chips , 2002, IEEE Micro.