This paper will describe a 32K x 8 CMOS EEPROM with on-chip ECC (Error Checking and Correction). Test features that enable effective testing of the on-chip ECC circuit and cell thrshold voltage will be described. A novel electrically programmable fuse circuit renders reliable implementation of redundancy and programmable optional features. The 5V full-featured [ I ] , [2] EEPROM with 64-byte page write mode has additional test features such as ECC disable, write cycle and program voltage (Vpp) ramp speed control, and write inhibit Vcc level adjustment. A double-poly, single-metal N-well CMOS technilagy with thin tunnel-oxide ( < I O O A O ) floating-gate cell is used to build the EEPROM. Minimum feature size 1 . 2 um is used to achieve 60 um' cell size and 68 mm' chip size. A 350A' composite interpoly dielectric is used to provide enhanced cell data retention characteristics. Far high voltage path, graded junction formed by double ion implantation is used to increase breakdown voltage. A modified Hamming code ECC scheme, having 4 parity cells per byte, is implemented with extended test features (Figure 1). Since most of endurance and data retention failures in a thin-oxide floating-gate EEPROM are caused by random defects in tunnel oxide, which can be corrected by the ECC scheme if not multiple in a byte, reliability of the EEPROM is drastically improved by the ECC scheme when the chip is properly tested. Parity code generator, core array data bits, and core array parity bits can be tested in separated modes. This separated testing is essential to production of highly reliable EEPROM and to direct evaluation of ECC impact an the chip reliability and yield. In the parity code check mode ( H 1 high), the parity generator is tested in a read speed by forming a closedloop circuit consisted of data-in buffer, parity code generator, and data-out buffer, as shown in dash lines in Figure 1. In this mode, when OE is low, input data is latched at the data-in buffer and corresponding parity code can be read from the data-out buffer. In the ECC disable made (H3 high), core array data bits are checked without correction, whereas core array parity bits are tested in the parity bit check mode (H2 high). Threshold voltage of each cell in the core array, used for precise monitoring of charge retention characteristic, is measured by excecuting a read cycle with external voltage applied to the cell control-gate line (Figure 2 ) . The external voltage is applied through pass transistors, the gates of which are connected to output of a high voltage follower circuit shown in Figure 3. Since the output of the high voltage follower circuit is grounded when input voltage is lower than the trip voltage, which is always about 3 Vt above Vcc, this threshold measurement scheme does not affect normal operation. In the threshold measurement mode, however, external voltage higher than Vcc can be transfer to the control-gate line by applying high voltage to the input of the follower circuit. A novel electrically programmable and erasable fuse circuit is shown in Figure 4. The four-cell bridge configuration enhances reliability of the fuse element significantly since the fuse element can tolerate a single cell failure out of its f o u r cells. This reliable fuse element is used for redundancy repairment, for user modes such as nonvolatile storage of software data protection state and ECC disable state, and for test modes including Vpp ramp speed control, write cycle time control, and write inhibit Vcc level adjustment. Read path design focuses on Vcc and temperature margin, on the minimization of dildt, and on the immunity to cell charge loss. Setting the cell control-gate line potential during read operation to the cell virgin threshold voltage(O.8V) provides the EEPROM inherent immunity to the cell charge loss or gain. Minimization of ground bouncing noise at high Vcc corner, without speed loss at low Vcc corner , is achieved by the use of depletion transistors at data-out buffers (Figure 5). The rise time of output driver gate node is insensitive to Vcc variation since it is controlled by saturation current of the depletion transistor. Photograph of the 256K EEPROM is shown in Figure 6. Read cycle waveforms at 5V, room temperature are shown in Figure 7.