Cost effective FPGA implementation for hard decision LDPC decoders

This paper proposes a QC-LDPC partial parallel architecture that implements a hard decision message passing algorithm based on Gallager-B decoding. The proposed architecture uses an optimized variable node unit, with adaptive threshold, suitable for irregular LDPC codes. We present implementation results for WiMAX rate 1/2 code for FPGA technology. These indicate a cost reduction of 2.5x in logic, and 25% in memory with respect to Min-Sum algorithm with 2 bits.

[1]  Manabu Hagiwara,et al.  Comment on "Quasi-Cyclic Low Density Parity Check Codes From Circulant Permutation Matrices" , 2009, IEEE Trans. Inf. Theory.

[2]  Robert G. Gallager,et al.  Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.

[3]  Lara Dolecek,et al.  Gallager B LDPC Decoder with Transient and permanent errors , 2013, 2013 IEEE International Symposium on Information Theory.

[4]  Hideki Imai,et al.  Reduced complexity iterative decoding of low-density parity check codes based on belief propagation , 1999, IEEE Trans. Commun..

[5]  Robert Michael Tanner,et al.  A recursive approach to low complexity codes , 1981, IEEE Trans. Inf. Theory.

[6]  Brendan J. Frey,et al.  Iterative Decoding of Compound Codes by Probability Propagation in Graphical Models , 1998, IEEE J. Sel. Areas Commun..

[7]  Bane Vasic,et al.  Performance analysis of faulty Gallager-B decoding of QC-LDPC codes , 2013, 2013 21st Telecommunications Forum Telfor (TELFOR).

[8]  Daehyun Kim,et al.  Improved hard-decision decoding LDPC Codec IP design , 2012, 2012 IEEE International Symposium on Circuits and Systems.

[9]  Valentin Savin,et al.  Chapter 4 – LDPC Decoders , 2014 .

[10]  Ioana Mot,et al.  Memory efficient FPGA implementation for flooded LDPC decoder , 2015, 2015 23rd Telecommunications Forum Telfor (TELFOR).

[11]  Todor Cooklev,et al.  Air Interface for Fixed Broadband Wireless Access Systems , 2004 .

[12]  An Pan,et al.  An Area-Efficient and Low-Power Multirate Decoder for Quasi-Cyclic Low-Density Parity-Check Codes , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.