A Modified CORDIC FPGA Implementation for Wave Generation

This paper presents a modified coordinate rotation digital computer (CORDIC) algorithm implemented in parallel architecture to generate sine and cosine waveform. Since CORDIC is a combination of only additions and shifts, it can be efficiently implemented in hardware. The proposed algorithm further approximates the way of computing rotation angle based on Taylor series in order to reduce the usage of Read-Only-Memory (ROM) table. Thus area and power is reduced due to partial usage of ROM storage. The precision remains the same as the original algorithm. The modified 32-bits pipeline CORDIC are implemented in Spartan XC3S500E device using Xilinx ISE 12.3 design suite. The result is compared with original CORDIC and Xilinx coregen in device utilization. It is shown that the logic usage is 31 FFs and 285 FFs less than the original design and Xilinx core, respectively. When compared with the original design, the signal power and total power reduction at 40 MHz clocks are 7.69 % and 1.35 %, respectively. The bit error remains at 10−8 dB level. The SNR of modified CORDIC is about 2 dB lower, which is acceptable in wave generation.