A $0.18{\mu}m$ CMOS 3.2-Gb/s 4-PAM Serial Link Receiver Using Current Mode Signaling

The design of a 3.2 Gb/s serial link receiver in CMOS process is presented. The major factors limiting the performance of high-speed links are transmission channel bandwidth, timing uncertainty. The design uses a multi-level signaling(4-PAM) to overcome these problems. Moreover, to increase data bit-rate and lower BER, we designed this circuit by using a current mode amplifier, Current-mode Logic(CML) sampling latches. The 4-PAM receiver achieves 3.2 Gb/s and BER is less than . The chip consumes 49 mA at 3.2 Gb/s from a 1.8-V supply.