System-level modeling and circuit design for low voltage CMOS equalizer for coaxial cable for video application

A new method of modeling coaxial cable frequency response with genetic algorithm was introduced. A system-level multi-stages adaptive equalizer model with QFB block was generated and tested with multiple cable models, pathological PRBS-23 data with data rate 1.5 GHz was used. This thesis also provided analysis of influences on output by using different parameters in simulations. Two adaptive equalizer circuits with different pre-amplifiers were implemented in GPDK 45 nm CMOS technology. Related simulations about adaptive ability, single stage compensation ability, and cascade stages compensation ability were completed. A tradeoff between output eye height and peak-to-peak jitter was discussed based on different simulations. Future work will be digital control circuit implementation, entire circuit fabrication, and testing.

[1]  Goldberg,et al.  Genetic algorithms , 1993, Robust Control Systems with Genetic Algorithms.

[2]  Hao Liu,et al.  Analog equalizers for high-speed wire-line data communications , 2010 .

[3]  M.H. Shakiba.  A 2.5 Gb/s adaptive cable equalizer , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[4]  Chuan Yi Tang,et al.  A 2.|E|-Bit Distributed Algorithm for the Directed Euler Trail Problem , 1993, Inf. Process. Lett..

[5]  Behzad Razavi,et al.  Design of Analog CMOS Integrated Circuits , 1999 .

[6]  R. Engelbrecht,et al.  DIGEST of TECHNICAL PAPERS , 1959 .

[7]  Tom V. Mathew.  Genetic Algorithm , 2022 .

[8]  Kyusun Choi,et al.  CMOS Ultrasound Transceiver Chip for High-Resolution Ultrasonic Imaging Systems , 2009, IEEE Transactions on Biomedical Circuits and Systems.

[9]  Martin J. Van Der Burgt.  Coaxial Cables and Applications , 2003 .

[10]  Francois Krummenacher,et al.  A 4-MHz CMOS Continuous-Time Filter with On-Chip Automatic Tuning , 1987, ESSCIRC '87: 13th European Solid-State Circuits Conference.

[11]  Chia-Hsin Wu,et al.  A 2 GHz CMOS variable-gain amplifier with 50 dB linear-in-magnitude controlled gain range for 10GBase-LX4 Ethernet , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[12]  Chih-Fan Liao,et al.  A 10Gb/s CMOS AGC Amplifier with 35dB Dynamic Range for 10Gb Ethernet , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[13]  Andreea Balteanu.  Coaxial Cable Equalization Techniques at 50-110 Gbps , 2010 .