Don't care sequences and the optimization of interacting finite state machines

The authors consider the nature of incomplete specifications for a finite state machine embedded in a network of sequential machines. They show how limited controllability and observability of component machines are expressed in quite different ways. For the input don't care sequences, a general solution was known. The authors present extensions to it, both in terms of topologies contemplated and in terms of applicability to larger designs. For the output don't care sequences, they provide a general theory based on the concept of information lossyness and present algorithms to address the related optimization problem in practical cases. The implementation of the proposed techniques in a program called SEQUOIA (sequential optimization of interacting automata) shows that the proposed approach is viable and effective. >

[1]  E. McCluskey Minimization of Boolean functions , 1956 .

[2]  Edward J. McCluskey Minimum-state sequential circuits for a restricted class of incompletely specified flow tables , 1962 .

[3]  Stephen H. Unger Flow Table Simplification-Some Useful Aids , 1965, IEEE Trans. Electron. Comput..

[4]  Frederick C. Hennie,et al.  Finite-state Models for Logical Machines , 1968 .

[5]  Stephen H. Unger,et al.  Asynchronous sequential switching circuits , 1969 .

[6]  Monty Newborn,et al.  The Simplification of Sequential Machines with Input Restrictions , 1972, IEEE Transactions on Computers.

[7]  Eduard Cerny,et al.  An Approach to Unified Methodology of Combinational Switching Circuits , 1977, IEEE Transactions on Computers.

[8]  Louise Trevillyan,et al.  Global Flow Analysis in Automatic Logic Design , 1986, IEEE Transactions on Computers.

[9]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[10]  Robert K. Brayton,et al.  MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Robert K. Brayton,et al.  Multi-level logic minimization using implicit don't cares , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Robert K. Brayton,et al.  Don't cares and global flow analysis of Boolean networks , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[13]  Srinivas Devadas,et al.  Approaches to Multi-Level Sequential Logic Synthesis , 1989, 26th ACM/IEEE Design Automation Conference.

[14]  Robert K. Brayton,et al.  An exact minimizer for Boolean relations , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[15]  Srinivas Devadas,et al.  Redundancies and don't cares in sequential logic synthesis , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[16]  Yahiko Kambayashi,et al.  The Transduction Method-Design of Logic Networks Based on Permissible Functions , 1989, IEEE Trans. Computers.

[17]  G. De Micheli,et al.  Synchronous logic synthesis: circuit specifications and optimization algorithms , 1990, IEEE International Symposium on Circuits and Systems.

[18]  W. Wolf An algorithm for nearly-minimal collapsing of finite-state machine networks , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[19]  Bill Lin,et al.  Minimization of symbolic relations , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[20]  Giovanni De Micheli,et al.  Synchronous logic synthesis: algorithms for cycle-time minimization , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  A. Richard Newton,et al.  MUSE: a multilevel symbolic encoding algorithm for state assignment , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[22]  Fabio Somenzi,et al.  Exact and heuristic algorithms for the minimization of incompletely specified state machines , 1994, Proceedings of the European Conference on Design Automation..

[23]  Robert K. Brayton,et al.  Retiming and resynthesis: optimizing sequential networks with combinational techniques , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[24]  Randal E. Bryant,et al.  Efficient implementation of a BDD package , 1991, DAC '90.