New CML latch structure for high speed prescaler design

This paper emphasizes on the design and analysis of current mode logic latches and their application in a frequency prescaler. Operation of a conventional CML latch is analyzed and a clock feedback structure is proposed for increased stability with reduced delay parameters. A low power design technique is presented for current mode logic frequency prescalers, which allows the master and slave latches to be merged together so that they use a single current source. This significantly reduces the power consumption and area and also offers lower terminal capacitances resulting in faster circuit operation.

[1]  Vladimir Stojanovic,et al.  Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems , 1999, IEEE J. Solid State Circuits.

[2]  Masayuki Mizuno,et al.  A GHz MOS adaptive pipeline technique using MOS current-mode logic , 1996, IEEE J. Solid State Circuits.

[3]  Payam Heydari,et al.  Design of ultra high-speed CMOS CML buffers and latches , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[4]  Bu-Cheol Jang,et al.  Design of A 1.8-V CMOS Frequency Synthesizer for WCDMA , 2002 .