Including higher-order moments of RC interconnections in layout-to-circuit extraction

This paper presents a reduction technique that transforms large RC networks into a minimal admittance network between the terminals, and that at the same time preserves the moments of each admittance exactly, up to any desired order. Any RC network can be dealt with, including capacitive coupling between lines. The technique presented has been incorporated in an efficient layout-to-circuit extractor using a scanline approach. The extracted moments can be used either in combination with Pade approximants for detailed timing-analysis, or simple RC models can be obtained directly by fitting to the extracted moments. The main advantage over AWE is that nodes are eliminated on the fly, thus reducing memory usage up to an order of magnitude.