Robust Soft Error Tolerant CMOS Latch Configurations

This paper presents a set of eight novel configurations for the design of single event soft error (SE) tolerant latches. Each latch uses a three-transistor building block called 1P-2N and its complementary block 2P-1N. It is shown that all proposed latches have better soft error rate (SER) performance as compared to the SE-tolerant latches reported till date. It is also shown that the proposed configurations provide a more relaxed tradeoff between SER and other specifications mainly delay, power dissipation and area. RTL implementation of a proposed latch is also shown to verify the behaviour subjected to the transient faults. The benefit of implementing a SE tolerant circuit in VHDL language is the feasibility to exhaustively check the immunity of the circuit against transient faults at every sensitive node by just writing simple boolean expressions of each element in the circuit. The proposed configurations and a few selected reported configurations have been also designed, laid out and post layout extracted in 90 nm CMOS logic technology. Post layout simulations have been performed on all proposed latch configurations with clock frequency of 500 MHz and performance comparison results are presented.

[1]  N. Seifert,et al.  Comparison of alpha-particle and neutron-induced combinational and sequential logic error rates at the 32nm technology node , 2009, 2009 IEEE International Reliability Physics Symposium.

[2]  B. M. Gordon,et al.  Supply and threshold voltage scaling for low power CMOS , 1997, IEEE J. Solid State Circuits.

[3]  T. Calin,et al.  Upset hardened memory design for submicron CMOS technology , 1996 .

[4]  K. Soumyanath,et al.  Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[5]  Hideo Ito,et al.  Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit , 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[6]  P. Hazucha,et al.  Impact of CMOS technology scaling on the atmospheric neutron soft error rate , 2000 .

[7]  R. Baumann.  Soft errors in advanced semiconductor devices-part I: the three radiation sources , 2001 .

[8]  R.C. Baumann,et al.  Radiation-induced soft errors in advanced semiconductor technologies , 2005, IEEE Transactions on Device and Materials Reliability.

[9]  Rong Luo,et al.  High Speed Soft-Error-Tolerant Latch and Flip-Flop Design for Multiple VDD Circuit , 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

[10]  Dan Alexandrescu,et al.  Low-Cost Highly-Robust Hardened Cells Using Blocking Feedback Transistors , 2008, 26th IEEE VLSI Test Symposium (vts 2008).

[11]  R. R. O'Brien,et al.  Collection of charge from alpha-particle tracks in silicon devices , 1983, IEEE Transactions on Electron Devices.

[12]  Cecilia Metra,et al.  High-Performance Robust Latches , 2010, IEEE Transactions on Computers.

[13]  Vivek De,et al.  Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process , 2004 .

[14]  Yong-Bin Kim,et al.  Soft-Error Hardening Designs of Nanoscale CMOS Latches , 2009, 2009 27th IEEE VLSI Test Symposium.

[15]  D. Rossi,et al.  Latch Susceptibility to Transient Faults and New Hardening Approach , 2007, IEEE Transactions on Computers.

[16]  Vojin G. Oklobdzija,et al.  Soft error filtered and hardened latch , 2009, 2009 IEEE 8th International Conference on ASIC.

[17]  Ken Choi,et al.  High Performance, Low Cost, and Robust Soft Error Tolerant Latch Designs for Nanoscale CMOS Technology , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.