Phase and Jitter Noise analysis of Phase Locks Loop (PLL) as Frequency Synthesiser

In this paper, we are evaluating the performance of the phase lock loop in the presence of phase noise and jitter noise. We are analysing the performance of PLL in one application of signal processing as frequency synthesiser. All the components of PLL contribute to the noise of the system. Two type of noise are presented that affect the performance of the system that are phase noise and jitter noise. Firstly, the Phase noise is generally used for representing short term random frequency variations of a signal. Non linear oscillators naturally produce high phase noise. Secondly, Jitter is generally used to refer to the time variation of a periodic signal in relation to the clock. The phase and jitter are the critical performance parameter to analysis the performance of the PLL. Simulation Result reveals that the performance of the PLL system is affected more by jitter noise compared to that of phase noise. Extensive simulation result is presented to demonstrate the effectiveness of the proposed techniques.

[1]  G.L. Fredendall,et al.  Automatic Frequency and Phase Control of Synchronization in Television Receivers , 1943, Proceedings of the IRE.

[2]  S.C. Gupta,et al.  Phase-locked loops , 1975, Proceedings of the IEEE.

[3]  Amit Mehrotra,et al.  Simulation and Modelling Techniques for Noise in Radio Frequency Integrated Circuits , 1999 .

[4]  Jianbo Sun,et al.  Modeling and Implementation of an All Digital Phase-Locked-Loop for Grid-Voltage Phase Detection , 2013, IEEE Transactions on Industrial Informatics.

[5]  J H Vincent,et al.  On some Experiments in which Two Neighbouring maintained Oscillatory Circuits affect a Resonating Circuit , 1919 .

[6]  Dong Yun,et al.  Phase-Locked Loop Circuit Design , 2011 .

[7]  Kyoohyun Lim,et al.  Low noise clock synthesizer design using optimal bandwidth , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[8]  Beomsup Kim,et al.  Optimal loop bandwidth design for low noise PLL applications , 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

[9]  Beomsup Kim,et al.  PLL/DLL system noise analysis for low jitter clock synthesizer design , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[10]  Aaas News,et al.  Book Reviews , 1893, Buffalo Medical and Surgical Journal.