DFM-aware fault model and ATPG for intra-cell and inter-cell defects

Yield improvement, yield ramp, and defect screening have been major areas of concern for the semiconductor industry as technology nodes have advanced. Much effort has been focused on capturing the defects missed by traditional stuck-at and transition delay fault model based testing. A majority of these un-modeled defects stems from features inside a standard cell or between two adjacent standard cells. Traditionally, critical area has been used as the manufacturability guideline to determine opens and shorts that should be targeted for test. This paper motivates a new paradigm — a design-for-manufacturability (DFM) hotspot-aware fault model to target intra-cell and inter-cell defects. The basic objective behind this approach is to bring in knowledge of manufacturing vulnerability in design layouts to weigh likelihood of occurrence of systematic defects. Recent technologies have standard cells much smaller than the lithography-driven optical diameter which means the cell's feature context is a key driver for DFM-driven fault sensitivity. This paper describes a novel automated flow for cell characterization that can be used to create patterns at the cell boundary for DFM-aware faults. The paper presents ATPG results for different DFM-aware faults, and analyzes the coverage gaps. Finally, the paper ends with a comparison with the cell-aware and dual-cell-aware fault models, and describes relative advantages and application scenarios.