LOGIC DESIGN TECHNIQUES FOR PROPAGATION LIMITED NETWORKS.

Abstract : Computationally efficient algorithms are presented for the clustering of the gates of an arbitrary network into pin-limited modules for minimum worst-cast network delay, assuming all delays are at module interfaces. Algorithms are presented for optimally locating clock-distribution terminals on a clock network having uncertain delays proportional to distance. The design of an economical signal-switching network is presented which, starting from the clear state, allows new arbitrary input/output terminal pairings to be made in arbitrary order. Another signal-switching network is described that permits an order-preserving transfer of a block of data among a set of fan-out-limited terminals with the minimum number of intermediate steps; an application is given to the block-transfer of data in a multiple-memory system. Several problems in the design and analysis of asynchronous sequential networks are examined, including the design of totally-sequential networks, given synchronously-derived specifications, the use of matrix-algebraic methods for NOR-element networks, consideration of the effect of input-delays in NOR-element asynchronous nets, and schemes for initializing controlled-logic networks, with and without loops. (Author)