Using Enhancement Mode GaN-on-Silicon Power FETs (eGaN® FETs)

A device’s cost effectiveness starts with leveraging existing production infrastructure with a process with few production steps. Depreciated, low resolution CMOS foundries are used in the fabrication of eGaN FETs. EPC’s process begins with silicon wafers upon which a thin layer of Aluminum Nitride (AlN) is grown to isolate the device structure from the substrate. On top of this, a layer of highly resistive Gallium Nitride is grown. This layer provides a foundation on which to build the GaN transistor. Aluminum Gallium Nitride (AlGaN) is applied to the GaN. This layer produces a physical strain, and because GaN is a piezoelectric material, the strain attracts electrons to the interface. This concentration of electrons is called a two-dimensional electron gas (2DEG). Further processing forms a depletion region under the gate, and metal layers are added to connect the three terminals, Gate, Drain, and Source. A cross section of this structure is depicted in Figure 1. This structure is repeated many times to form a power device. The end result is a fundamentally simple, elegant, cost effective solution for power switching. This device behaves similarly to silicon MOSFETs with some exceptions that will be explained in the following sections.