Reliability-aware cross-layer custom instruction screening
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Sied Mehdi Fakhraie | Saeed Safari | Bahareh J. Farahani | Ali Azarpeyvand | S. M. Fakhraie | S. Safari | A. Azarpeyvand
[1] Sied Mehdi Fakhraie,et al. CIVA: Custom instruction vulnerability analysis framework , 2012, 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).
[2] Kevin Skadron,et al. HotSpot: a compact thermal modeling methodology for early-stage VLSI design , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[3] Mehdi Kamal,et al. An architecture-level approach for mitigating the impact of process variations on extensible processors , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[4] Sied Mehdi Fakhraie,et al. Vulnerability Analysis for Custom Instructions , 2012, 2012 15th Euromicro Conference on Digital System Design.
[5] Yu Cao,et al. The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[6] Mehdi Kamal,et al. Timing variation-aware custom instruction extension technique , 2011, 2011 Design, Automation & Test in Europe.
[7] Joel Emer,et al. A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..
[8] Deming Chen,et al. Temperature aware statistical static timing analysis , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[9] Mircea R. Stan,et al. Modeling and analyzing NBTI in the presence of Process Variation , 2011, 2011 12th International Symposium on Quality Electronic Design.
[10] Koen Bertels,et al. The Instruction-Set Extension Problem: A Survey , 2008, ARC.
[11] Muhammad Shafique,et al. KAHRISMA: A Novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array Architecture , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).
[12] Farshad Firouzi,et al. Instruction reliability analysis for embedded processors , 2010, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems.
[13] Hyungmin Cho,et al. Cross-layer error resilience for robust systems , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[14] Srivaths Ravi,et al. Custom-instruction synthesis for extensible-processor platforms , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[15] S. P. Park,et al. Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance , 2007, ICCAD 2007.
[16] Mehdi Baradaran Tahoori,et al. Statistical analysis of BTI in the presence of process-induced voltage and temperature variations , 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).
[17] Fan Yang,et al. Statistical reliability analysis under process variation and aging effects , 2009, 2009 46th ACM/IEEE Design Automation Conference.
[18] Bo Yang,et al. Statistical prediction of circuit aging under process variations , 2008, 2008 IEEE Custom Integrated Circuits Conference.
[19] Jinjun Xiong,et al. Robust Extraction of Spatial Correlation , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.