Resource budgeting for reliability in reconfigurable architectures

SRAM-based reconfigurable architectures are susceptible to soft-errors. Accelerators in the reconfigurable fabric need to be protected by fault tolerance techniques such as modular redundancy and scrubbing. However, blindly applying these techniques to all accelerators leads to suboptimal performance due to overprotection. We introduce a metric, effective critical bits, to capture reliability impacting factors of the application. We present a method that performs budgeting of effective critical bits, i.e. decomposing the effective critical bits allowed by an application into effective critical bits allowed by its computational kernels and then into effective critical bits of their accelerated functions. This budgeting enables the runtime system to select appropriate accelerators and fault tolerance techniques to maximize the performance under a given target reliability. Compared to a strategy that duplicates all accelerators in the system, our method achieves up to 85% higher performance for a variety of reliability targets and soft-error rates.

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