Advanced process characterization of a 10nm Metal 1 Logic layer using light source modulation and monitoring

As ArF immersion lithography continues to be extended by adopting multi-patterning techniques, imaging requirements continue to become more stringent [1-3]. For multiple patterning based logic devices, the optimal printability is not only driven by the optimization of the optical proximity correction (OPC), but also by complex process factors, such as resist, exposure tool, and mask-related error performance levels. In addition the light source plays a crucial role; it has been widely demonstrated [4-8] how changes in the E95 bandwidth can significantly lead to changes in on wafer patterning due image contrast changes. Cymer has developed novel computational and experimental approaches to enable process characterization studies [9-11]. Using these techniques, simulations were used to assess how E95 bandwidth changes can erode the CDU budget on ≤ 20 nm logic features. Using the results of these simulations, experimental conditions were defined to study the on wafer impact of light source performance on an imec N10 Logic-type test vehicle via six different Metal 1 Logic features. The imaging metrics used to track patterning response are process window (PW), line width roughness (LWR), and local critical dimension uniformity (LCDU).