Analytical solution on interfacial reliability of 3-D through-silicon-via (TSV) containing dielectric liner

Abstract Interfacial reliability is a challenging issue in through-silicon-via (TSV) technique. To accurately investigate the interfacial reliability of TSV, this paper developed an analytical solution approach, in which the effects of the liner are considered. The validity of the analytical solution is executed by comparison with finite element simulation results. Results show that two approaches have good agreement, with a deviation within 10%, illustrating the validity of the analytical solution developed in this study. Then, using the developed analytical solution, the effects of via diameter, the liner thickness, and the liner materials of TSV on interfacial reliability are investigated with the steady-state energy release rate (ERR). Analytical results show that the steady-state ERR is not only determined by the coefficient of thermal expansion (CTE) mismatch between adjacent materials, but also affected by the products (E × CTE 2 ) of Young’s modulus (E) and CTE 2 of the liner. Liner materials with lower E × CTE 2 values will lead to lower steady-state ERR. Additionally, the combined effects of copper via diameter and liner thickness on ERR declare that the ERR highly depends on copper via diameter.

[1]  Leila Ladani,et al.  Numerical analysis of thermo-mechanical reliability of through silicon vias (TSVs) and solder interconnects in 3-dimensional integrated circuits , 2010 .

[2]  J. Y. Wu,et al.  CMP process development for the via-middle 3D TSV applications at 28nm technology node , 2012 .

[3]  Cher Ming Tan,et al.  Electromigration performance of Through Silicon Via (TSV) - A modeling approach , 2010, Microelectron. Reliab..

[4]  Chuan Seng Tan,et al.  Thermal mitigation using thermal through silicon via (TTSV) in 3-D ICs , 2009, 2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference.

[5]  Jian-Qiang Lu,et al.  3-D Hyperintegration and Packaging Technologies for Micro-Nano Systems , 2009, Proceedings of the IEEE.

[6]  H. Philipsen,et al.  Scalable Through Silicon Via with polymer deep trench isolation for 3D wafer level packaging , 2009, 2009 59th Electronic Components and Technology Conference.

[7]  Cheng-Ta Ko,et al.  Wafer-level bonding/stacking technology for 3D integration , 2010, Microelectron. Reliab..

[8]  Y.-L. Shen,et al.  Thermal expansion behavior of through-silicon-via structures in three-dimensional microelectronic packaging , 2012, Microelectron. Reliab..

[9]  A. G. Evans,et al.  Measurements of the debond energy for thin metallization lines on dielectrics , 1996 .

[10]  R. Tummala,et al.  Failure mechanisms and optimum design for electroplated copper Through-Silicon Vias (TSV) , 2009, 2009 59th Electronic Components and Technology Conference.

[11]  Shan Gao,et al.  Novel thinning/backside passivation for substrate coupling depression of 3D IC , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[12]  Edmund J. Sprogis,et al.  Wafer-level 3D integration technology , 2008, IBM J. Res. Dev..

[13]  Zheyao Wang,et al.  Low Capacitance Through-Silicon-Vias With Uniform Benzocyclobutene Insulation Layers , 2013, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[14]  F. Morancho,et al.  Filling of very deep, wide trenches by BenzoCycloButene polymer , 2009 .

[15]  Bart Vandevelde,et al.  Elimination Of The Axial Deformation Problem Of Cu-TSV In 3D Integration , 2010 .

[16]  Peter Ramm,et al.  3D System-on-Chip technologies for More than Moore systems , 2010, DTIP 2010.

[17]  Subramanian S. Iyer,et al.  3D integration review , 2011, Science China Information Sciences.

[18]  Suk-kyu Ryu,et al.  Thermal stress induced delamination of through silicon vias in 3-D interconnects , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[19]  Sung Kyu Lim,et al.  TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Suk-kyu Ryu,et al.  Thermo-mechanical reliability of 3-D ICs containing through silicon vias , 2009, 2009 59th Electronic Components and Technology Conference.

[21]  E. Beyne,et al.  Polymer Filling of Silicon Trenches for 3-D Through Silicon vias Applications , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[22]  Y. Y. Earmme,et al.  Experimental determination of thin film adhesion using 4 point bending specimen , 2001, Advances in Electronic Materials and Packaging 2001 (Cat. No.01EX506).

[23]  King-Ning Tu,et al.  Metallurgical challenges in microelectronic 3D IC packaging technology for future consumer electronic products , 2013 .

[24]  Xi Liu,et al.  Failure analysis of through-silicon vias in free-standing wafer under thermal-shock test , 2013, Microelectron. Reliab..

[25]  M. Koyanagi,et al.  Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections , 2006, IEEE Transactions on Electron Devices.

[26]  A. Evans,et al.  Matrix fracture in fiber-reinforced ceramics , 1986 .

[27]  D. Henry,et al.  Polymer filling of medium density through silicon via for 3D-packaging , 2009, 2009 11th Electronics Packaging Technology Conference.

[28]  K. N. Chen,et al.  Investigations of adhesion between Cu and Benzocyclobutene (BCB) polymer dielectric for 3D integration applications , 2011, 2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).

[29]  Andrew J. G. Strandjord,et al.  On the Mechanical Reliability of Photo-BCB-Based Thin Film Dielectric Polymer for Electronic Packaging Applications , 2000 .

[30]  Dongil Kwon,et al.  Interfacial reliability and micropartial stress analysis between TSV and CPB through NIT and MSA , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[31]  Zheyao Wang,et al.  Benzocyclobutene polymer filling of high aspect-ratio annular trenches for fabrication of Through-Silicon-Vias (TSVs) , 2012, Microelectron. Reliab..

[32]  Jae-Seok Yang,et al.  TSV stress aware timing analysis with applications to 3D-IC layout optimization , 2010, Design Automation Conference.

[33]  Mitsumasa Koyanagi,et al.  High-Density Through Silicon Vias for 3-D LSIs , 2009, Proceedings of the IEEE.

[34]  Suk-kyu Ryu,et al.  Thermal Stresses Analysis of 3‐D Interconnect , 2009 .

[35]  Liping Liu THEORY OF ELASTICITY , 2012 .

[36]  Suk-kyu Ryu,et al.  Impact of Near-Surface Thermal Stresses on Interfacial Reliability of Through-Silicon Vias for 3-D Interconnects , 2011, IEEE Transactions on Device and Materials Reliability.

[37]  T. Kurihara,et al.  Silicon interposer with TSVs (Through Silicon Vias) and fine multilayer wiring , 2008, 2008 58th Electronic Components and Technology Conference.