A CMOS Dissolved Wafer Process For Integrated P++ Microelectromechanical Systems

This paper presents a fabrication technolo for the integration of p++ microstructures with on-chip circuitry without restrictions upon device shape and size. It is a dissolved wafer technique that combines an electrochemical etch-stop for the circuitry with an impurity-based etch-stop for the microstructures, both of which are defined in an n-epi layer on a p-type Si wafer. A CMOS op. amp. has been integrated with p++ accelerometers using this process. It has a gain of 68 dB and an output swing within 0.2 V of its power supplies, unaffected by the wafer dissolution. The accelerometers have 3 /spl mu/m thick suspension beams and 15 /spl mu/m thick proof masses. The structural and electrical integrity of the fabricated devices demonstrates the success of the fabrication process.