A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique
暂无分享,去创建一个
Kenichi Okada | Akira Matsuzawa | Satoshi Kondo | Teerachot Siriburanon | Wei Deng | Dongsheng Yang | Tomohiro Ueno | K. Okada | A. Matsuzawa | W. Deng | Satoshi Kondo | T. Siriburanon | Tomohiro Ueno | Dongsheng Yang
[1] Wei Wang,et al. A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.
[2] Youngmin Park,et al. An All-Digital 12 pJ/Pulse IR-UWB Transmitter Synthesized From a Standard Cell Library , 2011, IEEE Journal of Solid-State Circuits.
[3] Deog-Kyoon Jeong,et al. Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator , 2014, IEEE Journal of Solid-State Circuits.
[4] Kenichi Okada,et al. A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration , 2014, IEEE Journal of Solid-State Circuits.
[5] Rob A. Rutenbar,et al. Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS , 2008, Proceedings of the IEEE.
[6] Ching-Che Chung,et al. An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.
[7] B. Helal,et al. A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop , 2008, IEEE Journal of Solid-State Circuits.
[8] Kenichi Okada,et al. A 0.022mm2 970µW dual-loop injection-locked PLL with −243dB FOM using synthesizable all-digital PVT calibration circuits , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[9] Un-Ku Moon,et al. Digitally synthesized stochastic flash ADC using only standard digital cells , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.
[10] Kenichi Okada,et al. 15.1 A 0.0066mm2 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).
[11] T. Morie,et al. A Design Method and Developments of a Low-Power and High-Resolution Multiphase Generation System , 2008, IEEE Journal of Solid-State Circuits.
[12] Ching-Che Chung,et al. A portable digitally controlled oscillator using novel varactors , 2005, IEEE Trans. Circuits Syst. II Express Briefs.
[13] Youngmin Park,et al. A Cyclic Vernier TDC for ADPLLs Synthesized From a Standard Cell Library , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.
[14] Kristofer S. J. Pister,et al. A 2.6psrms-period-jitter 900MHz all-digital fractional-N PLL built with standard cells , 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).
[15] Youngmin Park,et al. An all-digital PLL synthesized from a digital standard cell library in 65nm CMOS , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).
[16] Sheng Ye,et al. A multiple-crystal interface PLL with VCO realignment to reduce phase noise , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
[17] SeongHwan Cho,et al. A 14.2 mW 2.55-to-3 GHz Cascaded PLL With Reference Injection and 800 MHz Delta-Sigma Modulator in 0.13 $\mu$m CMOS , 2012, IEEE Journal of Solid-State Circuits.
[18] David D. Wentzloff,et al. An automatically placed-and-routed ADPLL for the medradio band using PWM to enhance DCO resolution , 2013, 2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).
[19] S.L.J. Gierkink,et al. Low-Spur, Low-Phase-Noise Clock Multiplier Based on a Combination of PLL and Recirculating DLL With Dual-Pulse Ring Oscillator and Self-Correcting Charge Pump , 2008, IEEE Journal of Solid-State Circuits.
[20] Nicola Da Dalt,et al. An Analysis of Phase Noise in Realigned VCOs , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.
[21] K. Muhammad,et al. All-digital PLL and transmitter for mobile phones , 2005, IEEE Journal of Solid-State Circuits.