Study of a VLSI Implementation of a Noise Reduction Algorithm for Digital Hearing Aids

A methodology for meeting the tight constraints in the physical realization of functional blocks for digital hearing aids was applied to the implementation of a noise reduction system based on lattice structures. This methodology fully exploits the fle xibility of custom VLSI design through a good interrelation among all the steps of the design. The emphasis was placed in the study of the fix ed point quantization effects to find the minimum number of bits and scaling required at every point of the algorithm. Based on these results, an estimation of the po wer consumption and required sil- icon area was done in the case of an implementation using a lo w power VLSI architecture.