Polymorphic Arrays: An Architecture for a Programmable Systolic Machine

We introduce the concept of PAM, Programmable Active Memory and present results obtained with our Perle-0 prototype board, featuring: A software silicon foundry for a 50K gate array, with a 50 milliseconds turn-around time. A 3000 one bit processors universal machine with an arbitrary interconnect structure specified by 400K bits of nano-code. A programmable hardware co-processor with an initial library including: a long multiplier, an image convolver, a data compressor, etc. Each of these hardware designs speeds up the corresponding software application by at least an order of magnitude.