Low Complexity LDPC for DVB Applications

Both constant and variable Forward Error Correcting (FEC) coding is provided by the DVB-S2 system. Variable FEC can be used to provide different levels of error protection according to applications & the channel condition to achieve Adaptive Coding. In this paper, we introduce an algebraic method for construction of well-structured variablerate Low Density Parity Check (LPDC) codes, enabling the system to switch between LDPC codes of different rates (9/10, 8/9, 5/6, 4/5, ...) using a single encoder and decoder structure. Well designed QC-LDPC codes can perform just as well as randomly constructed LDPC codes in terms of bit-error probability, block-error probability, and error floor, collectively. This paper describes BIBD based construction of QC-LDPC code using certain special classes of balanced incomplete block designs. A memory efficient implementation of Quasi-Cyclic LDPC decoder in a FPGA is discussed. For implementation of a LDPC decoder, a parity-check matrix should be stored in nonvolatile memory units which intensify the implementation issues. The idea discussed here is to reduce the memory requirements by real-time generation of the QC parity-check matrix instead of storing it. This is possible due to the circulant structure of QCLDPC codes. Synthesis results show that significant reduction in memory requirements is achievable.