Nonlinear behavioural model of charge pump PLLs

SUMMARY Despite the nonlinear nature of even the simplest versions of phase locked loops (PLLs), linear models are still used during the first phases of the design of modern PLLs. Even though the linear model may represent a crude approach, its use is justified by the fact that accurate numerical simulations often require a too large amount of CPU time, being PLLs by construction stiff circuits, characterised by very different time scales. This aspect has triggered the need for compact models that allow fast and accurate numerical simulations. The scientific literature numbers several models that have been developed with different approaches and tailored to different simulation environments. In this context, we propose a nonlinear model of a type-II PLL, which (1) considers both the switching behaviour of the phase/frequency detector and charge pump and the complex dynamics (including the presence of amplitude and phase noise) of the voltage controlled oscillator, (2) is compact and can be easily implemented in modern mixed analog/digital simulators as a behavioural block, and (3) allows the simulation of spurs owing to the nonlinearities of both the charge pump and the fractional frequency divider. Copyright © 2012 John Wiley & Sons, Ltd.

[1]  Pavan Kumar Hanumolu,et al.  Analysis of charge-pump phase-locked loops , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  Daniele D. Caviglia,et al.  Phase Noise Performances of a Cross-Coupled CMOS VCO with Resistor Tail Biasing , 2005, 2005 18th Symposium on Integrated Circuits and Systems Design.

[3]  H. Hedayati,et al.  Closed-Loop Nonlinear Modeling of Wideband$SigmaDelta$Fractional-$N$Frequency Synthesizers , 2006, IEEE Transactions on Microwave Theory and Techniques.

[4]  Floyd M. Gardner,et al.  Phaselock Techniques: Gardner/Phaselock Techniques , 2005 .

[5]  Eleonora Franchi,et al.  On the simulation of fast settling charge pump PLLs up to fourth order , 2011, Int. J. Circuit Theory Appl..

[6]  Eleonora Franchi,et al.  Quadrature VCOs based on direct second harmonic locking: Theoretical analysis and experimental validation , 2010, Int. J. Circuit Theory Appl..

[7]  Yuri A. Kuznetsov,et al.  An event-driven method to simulate Filippov systems with accurate computing of sliding motions , 2008, TOMS.

[8]  Yuri A. Kuznetsov,et al.  SlideCont: An Auto97 driver for bifurcation analysis of Filippov systems , 2005, TOMS.

[9]  Giambattista Gruosso,et al.  Periodic noise analysis of electric circuits: Artifacts, singularities and a numerical method , 2010 .

[10]  L. Chua,et al.  Chaos from phase-locked loops , 1988 .

[11]  R. Poujois,et al.  A new approach for noise simulation in transient analysis , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

[12]  Yves Leduc,et al.  Modeling and Characterization of the 3rd Order Charge-Pump PLL: a Fully Event-driven Approach , 1999 .

[13]  Tsutomu Sugawara,et al.  An efficient small signal frequency analysis method of nonlinear circuits with two frequency excitations , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Floyd M. Gardner,et al.  Phaselock techniques , 1984, IEEE Transactions on Systems, Man, and Cybernetics.

[15]  Angelo Brambilla,et al.  Frequency warping in time-domain circuit simulation , 2003 .

[16]  F. Gardner,et al.  Charge-Pump Phase-Lock Loops , 1980, IEEE Trans. Commun..

[17]  G. Coram.  A simple 2-D oscillator to determine the correct decomposition of perturbations into amplitude and phase noise , 2001 .

[18]  Edgar Sánchez-Sinencio,et al.  A Stable Loss Control Feedback Loop for VCO Amplitude Tuning , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[19]  Zuoding Wang.  An analysis of charge-pump phase-locked loops , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[20]  Federico Bizzarri,et al.  Steady State Computation and Noise Analysis of Analog Mixed Signal Circuits , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[21]  Bram Nauta,et al.  Architectures for RF Frequency Synthesizers , 2002 .

[22]  Michael H. Perrott.  Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits , 2002, DAC '02.

[23]  Daniele D. Caviglia,et al.  Differential Cross-Coupled CMOS VCOs with Resistive and Inductive Tail Biasing , 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

[24]  Poras T. Balsara,et al.  Event-driven Simulation and modeling of phase noise of an RF oscillator , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[25]  A. Demir,et al.  Phase noise in oscillators: a unifying theory and numerical methods for characterization , 2000 .

[26]  Harry Dankowicz,et al.  TC-HAT: A Novel Toolbox for the Continuation of Periodic Trajectories in Hybrid Dynamical Systems , 2008, SIAM J. Appl. Dyn. Syst..

[27]  Jacob K. White,et al.  Efficient AC and noise analysis of two-tone RF circuits , 1996, DAC '96.

[28]  Chia-Yu Yao,et al.  An Application of the Second-Order Passive Lead–Lag Loop Filter for Analog PLLs to the Third-Order Charge-Pump PLLs , 2008, IEEE Transactions on Industrial Electronics.

[29]  Somnath Maity,et al.  Bifurcation Analysis of PWM-1 Voltage-Mode-Controlled Buck Converter Using the Exact Discrete Model , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[30]  Leon O. Chua,et al.  Bifurcation diagrams and fractal brain boundaries of phase-locked loop circuits , 1990 .

[31]  Alan R. Champneys,et al.  Bifurcations in piecewise-smooth dynamical systems: Theory and Applications , 2007 .

[32]  Behzad Razavi.  Phase-Locking In High-Performance Systems , 2003 .

[33]  A. Hindmarsh,et al.  CVODE, a stiff/nonstiff ODE solver in C , 1996 .

[34]  Giambattista Gruosso,et al.  Robust Harmonic-Probe Method for the Simulation of Oscillators , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[35]  Daniele D. Caviglia,et al.  Improved Small-Signal Analysis for Circuits Working in Periodic Steady State , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[36]  Leon O. Chua,et al.  Chaos from phase-locked loops. High-dissipation case , 1989 .

[37]  Kishore Singhal,et al.  Computer Methods for Circuit Analysis and Design , 1983 .

[38]  Giambattista Gruosso,et al.  FSSA: Fast Steady-State Algorithm for the Analysis of Mixed Analog/Digital Circuits , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[39]  Lars C. Jansson,et al.  A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation , 2004, IEEE Journal of Solid-State Circuits.

[40]  Salvatore Levantino,et al.  Integrated Frequency Synthesizers for Wireless Systems , 2007 .

[41]  Paolo Maffezzoni,et al.  Time‐domain analysis of phase‐noise and jitter in oscillators due to white and colored noise sources , 2012, Int. J. Circuit Theory Appl..

[42]  J. Yorke,et al.  Bifurcations in one-dimensional piecewise smooth maps-theory and applications in switching circuits , 2000 .

[43]  A. Suarez,et al.  General envelope-transient formulation of phase-locked loops using three time scales , 2004, IEEE Transactions on Microwave Theory and Techniques.

[44]  Michael H. Perrott.  Behavioral Simulation of Fractional-N Frequency Synthesizers and Other PLL Circuits , 2002, IEEE Des. Test Comput..

[45]  Luca Selmi,et al.  Comprehensive Behavioral Modeling of Conventional and Dual-Tuning PLLs , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[46]  Carlo Samori,et al.  Spectrum folding and phase noise in LC tuned oscillators , 1998 .