Comparative analysis of redundancy schemes for soft-error detection in low-cost space applications

Single-Event Effects are an increasingly important issue in electronic circuits due to technology scaling, efficient error detection schemes are thus required for circuits dedicated to radiative environments, such as in space applications. This work shows that the widespread spatial and temporal redundancy schemes exhibit widely different performances depending on technology, environment and circuit architecture parameters. Following these results, three new redundancy schemes are proposed and compared: one of them, the Forward Temporal Redundancy, stands out as it achieves full error detection with limited timing penalty at only 100% sequential and 45% combinational overheads for a benchmark pipelined MIPS microprocessor.

[1]  J. Barth,et al.  Space, atmospheric, and terrestrial radiation environments , 2003 .

[2]  Cheng-Wen Wu,et al.  An integrated ECC and redundancy repair scheme for memory reliability enhancement , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

[3]  Daniela Fischer,et al.  Digital Design And Computer Architecture , 2016 .

[4]  B. Narasimham,et al.  Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies , 2007, IEEE Transactions on Nuclear Science.

[5]  J. Barth,et al.  Model for Cumulative Solar Heavy Ion Energy and Linear Energy Transfer Spectra , 2007, IEEE Transactions on Nuclear Science.

[6]  Lorenzo Alvisi,et al.  Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.

[7]  R.C. Baumann,et al.  Radiation-induced soft errors in advanced semiconductor technologies , 2005, IEEE Transactions on Device and Materials Reliability.

[8]  Trevor Mudge,et al.  Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[9]  David Bol,et al.  A Partial Reconfiguration-based scheme to mitigate Multiple-Bit Upsets for FPGAs in low-cost space applications , 2015, 2015 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC).

[10]  P.H. Eaton,et al.  Digital Single Event Transient Trends With Technology Node Scaling , 2006, IEEE Transactions on Nuclear Science.

[11]  Luigi Carro,et al.  Fault-Tolerance Techniques for SRAM-Based FPGAs (Frontiers in Electronic Testing) , 2006 .

[12]  Jeffrey T. Draper,et al.  DEC ECC design to improve memory reliability in Sub-100nm technologies , 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.