VLSI Implementation of 8051 MCU with Decoupling Capacitor for IC-EMC

In recent years, several new methods for IC-level electromagnetic compatibility (EMC) testing have been introduced. Therefore, a handy vehicle for IC-EMC testing is required to validate the effectiveness of the new IC-EMC testing methods. This paper proposes an 8051 MCU for IC-EMC testing platform with in-system programming (ISP) and decoupling capacitor (decap) functions. In order to reduce the EMI and improve the EMC properties for the 8051 MCU, decoupling capacitors (decaps) are added to the integrated circuit (IC) design flow. Chip-level design and fabrication technology are fundamental and cost-effective solutions to this issue. A cell-based design flow is used for chip implementation; specifically, TSMC 90-nm technology is used to implement the present chip via the National Chip Implementation Center. This study will implement two 8051 MCU chips: one that internally comprises a large number of decaps, and another that comprises no decaps. We also implemented an IC-EMC testing platform composed of a multifunction test board and several off-board probes that were fabricated according to IEC 61967 and IEC 62132 standards. The platform demonstrates a method for using the proposed two 8051 chips in EMC testing, and we reveal the results of its EMC performance. Finally, this study simulates the EMC properties, compares the two 8051 MCU chips, conducts static or dynamic analyses for the chips in a power network, and measures the EMC improvements.