Adaptive test program generation: planning for the unplanned

Simulation of automatically-generated test programs is the primary means for verifying complex hardware designs and random test program generators therefore play a major role in the verification process of micro-processors. The input for a test program generator is typically an abstract specification-a template-of the tests to be generated. Due to randomness, generators often encounter situations that were not anticipated when the test specification was written. We introduce the concept of adaptive test program generation, which is designed to handle these unforeseen situations. We propose a technique that defines unexpected events together with their alternative program specifications. When an event is detected, its corresponding alternative specification is injected into the test program.

[1]  P. Konas,et al.  Code generation and analysis for the functional verification of microprocessors , 1996, 33rd Design Automation Conference Proceedings, 1996.

[2]  A. K. Chandra,et al.  Constraint solving for test case generation: a technique for high-level design verification , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[3]  Aharon Aharon,et al.  Test Program Generation for Functional Verification of PowePC Processors in IBM , 1995, 32nd Design Automation Conference.

[4]  Avi Ziv,et al.  Using a constraint satisfaction formulation and solution techniques for random test program generation , 2002, IBM Syst. J..

[5]  Daniel Geist,et al.  A methodology for the verification of a “system on chip” , 1999, DAC '99.

[6]  Carl Ramey,et al.  Functional verification of a multiple-issue, out-of-order, superscalar Alpha processor-the DEC Alpha 21264 microprocessor , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[7]  Allon Adir,et al.  Improving test quality through resource reallocation , 2001, Sixth IEEE International High-Level Design Validation and Test Workshop.

[8]  Anoosh Hosseini,et al.  Code generation and analysis for the functional verification of micro processors , 1996, DAC '96.

[9]  Laurent Fournier,et al.  Functional verification methodology for microprocessors using the Genesys test-program generator. Application to the x86 microprocessors family , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).