Nonlinear effects of TSV and harmonic generation
暂无分享,去创建一个
Joungho Kim | Jun So Pak | Jonghyun Cho | Kunwoo Park | Joungho Kim | Jonghyun Cho | Joohee Kim | J. Pak | Hyungdong Lee | Kunwoo Park | Junho Lee | Junho Lee | Joohee Kim | Hyungdong Lee
[1] Junho Lee,et al. High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV) , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.
[2] W. Dehaene,et al. Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs , 2010, IEEE Transactions on Electron Devices.
[3] Junho Lee,et al. I/O power estimation and analysis of high-speed channels in through-silicon via (TSV)-based 3D IC , 2010, 19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems.
[4] J. Meindl,et al. Limits on silicon nanoelectronics for terascale integration. , 2001, Science.
[5] Junho Lee,et al. Modeling and Analysis of Through-Silicon Via (TSV) Noise Coupling and Suppression Using a Guard Ring , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.
[6] W. Dehaene,et al. Through-Silicon-Via Capacitance Reduction Technique to Benefit 3-D IC Performance , 2010, IEEE Electron Device Letters.
[7] Sanjay Raman,et al. Large-signal analysis of MOS varactors in CMOS -Gm LC VCOs , 2003, IEEE J. Solid State Circuits.
[8] Sanjay Raman,et al. Large-signal analysis of MOS varactors in CMOS -G/sub m/ LC VCOs , 2003 .
[9] D. Schroder. Semiconductor Material and Device Characterization , 1990 .
[10] Katsuyuki Sakuma,et al. Three-dimensional silicon integration , 2008, IBM J. Res. Dev..
[11] Joungho Kim,et al. Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias (TSV) , 2007, 2007 Proceedings 57th Electronic Components and Technology Conference.