A non-enumerative path delay fault simulator for sequential circuits

We extend the path status graph (PSG) method of delay fault simulation to sequential circuits. By devising a layered PSG and restricting the number of time-frames over which a fault must be detected, we preserve the non-enumerative nature of the simulation algorithm. The program is capable of simulating a wide variety of circuits (synchronous, asynchronous, multiple-clock and tri-state logic.) Both rated and variable clock modes, as well as robust, non-robust or functional sensitization detection options, are available. The simulation can be stopped and restarted through a check pointing facility. The program can target any given list of paths. This path list can also be generated by the program based on user-selectable criteria (all paths, longest paths, paths between certain I/O pairs, etc.) User reports include a histogram of path coverage versus path length. Detected and undetected path data remain implicit in the PSG and can be retrieved through post-processing commands. Due to its non-enumerative stature, the program can process most production level digital logic circuits.

[1]  Irith Pomeranz,et al.  An efficient non-enumerative method to estimate path delay fault coverage , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[2]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[3]  Vishwani D. Agrawal,et al.  An exact non-enumerative fault simulator for path-delay faults , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[4]  Janak H. Patel,et al.  Improving a nonenumerative method to estimate path delay fault coverage , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Sandeep K. Gupta,et al.  A Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits , 1996, IEEE Trans. Computers.

[6]  Soumitra Bose,et al.  A rated-clock test method for path delay faults , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[7]  Irith Pomeranz,et al.  SPADES-ACE: a simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Vishwani D. Agrawal,et al.  On variable clock methods for path delay testing of sequential circuits , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Vishwani D. Agrawal,et al.  Path delay fault simulation algorithms for sequential circuits , 1992, Proceedings First Asian Test Symposium (ATS `92).

[10]  Soumitra Bose,et al.  Path delay fault simulation of sequential circuits , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[11]  Vishwani D. Agrawal,et al.  Path delay testing: variable-clock versus rated-clock , 1998, Proceedings Eleventh International Conference on VLSI Design.

[12]  S. Davidson,et al.  The architecture of the GenTest sequential test generator , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.