Low complexity soft-decision demapper for high order modulation of DVB-S2 system

This paper presents an efficient soft-decision demapper interface and a low complexity demapper for high-order modulation scheme. The proposed soft-decision demapper interface can operate at a symbol rate and replace the parallel to serial converter by locating between the M-PSK demodulator and the soft-decision demapper. In addition, the proposed soft-decision demapper can reduce the hardware complexity by reusing the multipliers. Moreover, the proposed demapper can support high-order modulation modes. The proposed architectures have been thoroughly verified using a FPGA board having the the Xilinxtrade Virtex II.

[1]  Duk Gun Choi,et al.  Low Density Parity Check Decoding Algorithm for Multi-level Modulation Scheme , 2005, 2005 Asia-Pacific Conference on Communications.

[2]  Seung Hyun Choi,et al.  The Mapping and demmaping algorithms for high order modulation of DVB-S2 systems , 2006, 2006 Asia-Pacific Conference on Communications.

[3]  In Ki Lee,et al.  Multi-level modulation LDPC Decoding Algorithm for New Generation DVB-S2 system , 2006 .

[4]  Min-Kyu Kim,et al.  Software implementation of TPEG decoder on a T-DMB using X-PAD , 2008, 2008 International SoC Design Conference.

[5]  Prof.Dr.-Ing. Ulrich Reimers.  Digital Video Broadcasting (DVB) , 2001, Springer Berlin Heidelberg.