Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths

This brief presents the unique capabilities of the multimode Dual Mode Logic (DML) design technique to define run-time adaptive datapaths to overcome process and environmental (i.e., temperature and voltage) variations. A proof-of-concept benchmark circuit is designed and fabricated in 65 nm technology. Measurements on 10 test chips, while considering supply voltages spanning 0.6V to 1.2V and temperature variations ranging from −40 °C to 125 °C confirm the effectiveness of this approach to compensate for severe process, voltage and temperature (PVT) variations.

[1]  James Tschanz,et al.  Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating , 2017, IEEE Journal of Solid-State Circuits.

[2]  David Blaauw,et al.  A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation , 2011, IEEE Journal of Solid-State Circuits.

[3]  Chingwei Yeh,et al.  Towards Process Variation-Aware Power Gating , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Olivier Billoint,et al.  A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[5]  Olivier Billoint,et al.  A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking , 2015, IEEE Journal of Solid-State Circuits.

[6]  David M. Bull,et al.  RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance , 2009, IEEE Journal of Solid-State Circuits.

[7]  Dennis Sylvester,et al.  Razor-lite: A side-channel error-detection register for timing-margin recovery in 45nm SOI CMOS , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[8]  David Blaauw,et al.  Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction , 2013, IEEE Journal of Solid-State Circuits.

[9]  Alexander Fish,et al.  Logical Effort for CMOS-Based Dual Mode Logic Gates , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Alexander Fish,et al.  Process Variation-Aware Datapath Employing Dual Mode Logic , 2018, 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

[11]  A.P. Chandrakasan,et al.  Nanometer MOSFET Variation in Minimum Energy Subthreshold Circuits , 2008, IEEE Transactions on Electron Devices.

[12]  Alexander Fish,et al.  An 88-fJ/40-MHz [0.4 V]–0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 $\times$ 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI , 2019, IEEE Journal of Solid-State Circuits.

[13]  David Blaauw,et al.  iRazor: Current-Based Error Detection and Correction Scheme for PVT Variation in 40-nm ARM Cortex-R4 Processor , 2018, IEEE Journal of Solid-State Circuits.

[14]  Andreas Peter Burg,et al.  DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment , 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.

[15]  Alexander Fish,et al.  Design Flow and Characterization Methodology for Dual Mode Logic , 2015, IEEE Access.

[16]  Massimo Alioto,et al.  Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[17]  Azad Naeemi,et al.  System-Level Variation Analysis for Interconnection Networks at Sub-10-nm Technology Nodes Using Multiple Patterning Techniques , 2015, IEEE Transactions on Electron Devices.