A 135mV 0.13μW process tolerant 6T subthreshold DTMOS SRAM in 90nm technology

Cell stability and tolerance to process variation are of primary importance in subthreshold SRAMs. We propose a DTMOS based 6T SRAM suitable for subthreshold operation. For variation tolerant memory peripheral circuitry, we apply beta-ratio modulation technique. DTMOS SRAM array fabricated in 90 nm technology operates down to 135 mV consuming 0.13 muW at 750 Hz. The proposed SRAM achieves 200% improvement in read static noise margin at iso-area compared to the conventional 6T SRAM at a supply voltage of 200 mV.

[1]  Masashi Horiguchi,et al.  Review and future prospects of low-voltage RAM circuits , 2003, IBM J. Res. Dev..

[2]  Anna W. Topol,et al.  Stable SRAM cell design for the 32 nm node and beyond , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[3]  J. Meindl,et al.  The impact of intrinsic device fluctuations on CMOS SRAM cell stability , 2001, IEEE J. Solid State Circuits.

[4]  James Tschanz,et al.  Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[5]  A. Chandrakasan,et al.  A 180mV FFT processor using subthreshold circuit techniques , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[6]  Kaushik Roy,et al.  Ultra-low power digital subthreshold logic circuits , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[7]  K. Takeda,et al.  A read-static-noise-margin-free SRAM cell for low-V/sub dd/ and high-speed applications , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[8]  S. Natarajan,et al.  A high density, low leakage, 5T SRAM for embedded caches , 2004, Proceedings of the 30th European Solid-State Circuits Conference.

[9]  Jason Liu,et al.  A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[10]  A. Chandrakasan,et al.  A 256kb Sub-threshold SRAM in 65nm CMOS , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[11]  Kaushik Roy,et al.  Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  L.T. Clark,et al.  An Ultra-Low-Power Memory With a Subthreshold Power Supply Voltage , 2006, IEEE Journal of Solid-State Circuits.

[13]  Masahiro Nomura,et al.  A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications , 2006, IEEE Journal of Solid-State Circuits.

[14]  Hiroshi Kawaguchi,et al.  Dynamic leakage cut-off scheme for low-voltage SRAM's , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).