Field Effect Diode (FED): A novel device for ESD protection in deep sub-micron SOI technologies

In this paper the authors present the field effect diode (FED) as a novel device with a new approach for ESD protection in SOI. Device parameters are identified and optimized to achieve optimum ON and OFF behavior. Furthermore, the authors present two ways the FED can be used in an ESD protection scheme: in I/O clamping and in a high-voltage supply clamp

[1]  Vivek Subramanian,et al.  Sub-50nm FinFET : PMOS , 1999 .

[2]  Robin Williams,et al.  Electrostatic discharge protection in silicon-on-insulator technology , 1999, 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).

[3]  Chenming Hu,et al.  Sub 50-nm FinFET: PMOS , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[4]  C. Duvvury,et al.  A fail-safe ESD protection circuit with 230 fF linear capacitance for high-speed/high-precision 0.18 /spl mu/m CMOS I/O application , 2002, Digest. International Electron Devices Meeting,.

[5]  K. Gopalakrishnan,et al.  I-MOS: a novel semiconductor device with a subthreshold slope lower than kT/q , 2002, Digest. International Electron Devices Meeting,.

[6]  G. Burbach,et al.  Taking SOI substrates and low-k dielectrics into high-volume microprocessor production , 2003, IEEE International Electron Devices Meeting 2003.

[7]  M. Muhammad,et al.  Human Body Model ESD protection concepts in SOI and bulk CMOS at the 130 nm node , 2003, 2003 IEEE International Conference on SOI.

[8]  Farshid Raissi,et al.  High-speed digital family using field effect diode , 2003 .

[9]  D. Mocuta,et al.  High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[10]  Benjamin Van Camp,et al.  SCR based ESD protection in nanometer SOI technologies , 2005, 2005 Electrical Overstress/Electrostatic Discharge Symposium.

[11]  A. Marshall,et al.  ESD evaluation of the emerging MuGFET technology , 2005, 2005 Electrical Overstress/Electrostatic Discharge Symposium.

[12]  G. Burbach,et al.  A novel self-aligned substrate-diode structure for SOI technologies , 2005, 2005 IEEE International SOI Conference Proceedings.

[13]  C. Duvvury,et al.  Analysis of ESD protection components in 65nm CMOS technology: Scaling perspective and impact on ESD design window , 2005, 2005 Electrical Overstress/Electrostatic Discharge Symposium.