Low- and ultra low-power arithmetic units: design and comparison
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[1] Mary Jane Irwin,et al. Area-time-power tradeoffs in parallel adders , 1996 .
[2] Vojin G. Oklobdzija,et al. On Implementing Addition in VLSI Technology , 1988, J. Parallel Distributed Comput..
[3] Vojin G. Oklobdzija,et al. Some optimal schemes for ALU implementation in VLSI technology , 1985, 1985 IEEE 7th Symposium on Computer Arithmetic (ARITH).
[4] Vojin G. Oklobdzija,et al. High-performance system design : circuits and logic , 1999 .
[5] V.G. Oklobdzija,et al. Energy minimization method for optimal energy-delay extraction , 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).
[6] M. Lehman,et al. Skip Techniques for High-Speed Carry-Propagation in Binary Arithmetic Units , 1961, IRE Trans. Electron. Comput..
[7] Orest J. Bedrij. Carry-Select Adder , 1962, IRE Trans. Electron. Comput..
[8] Victor V. Zyuban,et al. Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels , 2002, ISLPED '02.
[9] Jack Sklansky,et al. Conditional-Sum Addition Logic , 1960, IRE Trans. Electron. Comput..
[10] Bart R. Zeydel,et al. Low-power aspects of different adder topologies , 2003, The Thrity-Seventh Asilomar Conference on Signals, Systems & Computers, 2003.
[11] I. Sutherland,et al. Logical Effort: Designing Fast CMOS Circuits , 1999 .
[12] Stamatis Vassiliadis,et al. A static low-power, high-performance 32-bit carry skip adder , 2004, Euromicro Symposium on Digital System Design, 2004. DSD 2004..
[13] Earl E. Swartzlander,et al. Optimizing Arithmetic Elements For Signal Processing , 1992, Workshop on VLSI Signal Processing.
[14] Sanu Mathew,et al. Comparison of high-performance VLSI adders in the energy-delay space , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[15] R. Krishnamurthy,et al. A 4 GHz 130 nm address generation unit with 32-bit sparse-tree adder core , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).
[16] Akhilesh Tyagi,et al. A Reduced-Area Scheme for Carry-Select Adders , 1993, IEEE Trans. Computers.
[17] Harold S. Stone,et al. A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973, IEEE Transactions on Computers.