论文信息 - SEU mitigation testing of Xilinx Virtex II FPGAs

SEU mitigation testing of Xilinx Virtex II FPGAs

SRAM-based reconfigurable programmable logic is widely used in commercial applications and occasionally used in space flight applications because of susceptibility to single-event upset (SEU). Upset detection and mitigation schemes have been tested on the Xilinx Virtex II X-2V1000 in heavy-ion and proton irradiation to control the accumulation of SEUs and to mitigate their effects on the intended operation. Non-intrusive upset detection and partial reconfiguration in combination with TMR can repair the design to maintain state information. In-beam results on a simple test design demonstrate the effectiveness of these methods when used together.

C. Carmichael | R. Koga | G. M. Swift | C. Yui | Jeffrey S. George

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