A low power multiplier using adiabatic charging binary decision diagram circuit

An adiabatic charging binary decision diagram circuit (AC-BDD) is proposed that uses pass transistor logic based on a BDD and is operated by four power clocks. The AC-BDD circuit has the characteristics of a gate-level pipeline. Also proposed is a simplified switched capacitor regenerator that operates stably at any time even if the load capacitance changes variously. An 8×8 bit multiplier was designed using 0.25-µm CMOS/SIMOX (Complementary MOS/Separation by IMplanted OXygen) technology to confirm charging recovery. We found that the multiplier operates at 0.2 V and 1 MHz and its power consumption can be decreased to less than 10% that of CMOS logic.