Transient analysis of submicron CMOS latchup with a physical criterion

Abstract A new physical criterion and an analytical timing model for transient latchup in a p-n-p-n structure are developed and verified. In the new physical transient latchup criterion, two new parameters called the large-signal transient current gains of the parasitic vertical and lateral BJTs in the p-n-p-n structure are defined. If their product rather than the forward beta-gain product becomes larger than unity right after triggering and remains larger than unity, the latchup occurs. With the piecewise-linearized device currents of the parasitic BJTs and the averaged junction depletion and diffusion capacitances in the p-n-p-n structure, the large-signal transient current gains are derived as functions of time and device parameters. Moreover, the dynamic behaviors and the associated timing of transient latchup can also be fully characterized. Model calculation results using the developed criterion and timing model agree very well with both SPICE simulation and experimental results. Thus the developed criterion and timing model can be applied to transient latchup analysis and prediction in CMOS ICs.