A dynamic comparator with analog offset calibration for biomedical SAR ADC applications

A new ultra-low voltage and power digital comparator using analog offset calibration technique is presented in this paper. The comparator's input transistors are working in subthreshold region for the entire input range and is used as a zero crossing detector for the analog offset calibration technique. Realized using GLOBALFOUNDRIES 0.18μm CMOS process technology, at the voltage supply of 0.7V and 1MHz clock frequency, the standalone comparator dissipates 153nW but increasing to 494nW with calibration function. For voltage supply down to 0.4V and 20 kHz clock, the single comparator dissipates only 8.054nW. The calibration circuit is capable of reducing a 20mV of input-referred dc offset down to 655.3μV, making it suitable for 10-bit biomedical SAR ADC applications.

[1]  R. Jacob Baker,et al.  CMOS Circuit Design, Layout, and Simulation , 1997 .

[2]  Huazhong Yang,et al.  A 250KS/s, 0.8V ultra low power successive approximation register ADC using a Dynamic rail-to-rail comparator , 2010, IEICE Electron. Express.

[3]  Achim Graupner.  A Methodology for the Offset- Simulation of Comparators , 2006 .

[4]  Jia Chen,et al.  A low-kickback-noise latched comparator for high-speed flash analog-to-digital converters , 2005, IEEE International Symposium on Communications and Information Technology, 2005. ISCIT 2005..

[5]  Karim Abdelhalim,et al.  A Nanowatt Successive Approximation ADC with Offset Correction for Implantable Sensor Applications , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[6]  Pak Kwong Chan,et al.  An ultra low-power Successive Approximation ADC using an offset-biased auto-zero comparator , 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.