Worst case crosstalk noise for nonswitching victims in high-speed buses
暂无分享,去创建一个
[1] Trevor York,et al. Book Review: Principles of CMOS VLSI Design: A Systems Perspective , 1986 .
[2] Ken Tseng,et al. Static noise analysis with noise windows , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[3] P.D. Gross,et al. Determination of worst-case aggressor alignment for delay calculation , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).
[4] Kaushik Roy,et al. Timed pattern generation for noise-on-delay calculation , 2002, DAC '02.
[5] Malgorzata Marek-Sadowska,et al. Aggressor alignment for worst-case crosstalk noise , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[6] John Lillis,et al. Interconnect Analysis and Synthesis , 1999 .
[7] Lawrence T. Pileggi,et al. IC analyses including extracted inductance models , 1999, DAC '99.
[8] Yu Cao,et al. Effects of global interconnect optimizations on performance estimation of deep submicron design , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).
[9] John K. Ousterhout. Switch-Level Delay Models for Digital MOS VLSI , 1984, 21st Design Automation Conference Proceedings.
[10] Lei He,et al. An efficient inductance modeling for on-chip interconnects , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).
[11] Lawrence T. Pileggi,et al. A Gate-Delay Model for High-Speed CMOS Circuits , 1994, 31st Design Automation Conference.
[12] Neil Weste,et al. Principles of CMOS VLSI Design , 1985 .
[13] Lei He,et al. Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization , 2000, ISPD '00.
[14] Min Xu,et al. An efficient model for frequency-dependent on-chip inductance , 2001, GLSVLSI '01.