DRAM Bandwidth Optimized Design for High-Throughput Video Decoder Chips

i-Abstract The last two decades have witnessed the tremendous advances in video coding technologies. From MPEG-1/2/4 to H.264/AVC, AVS, etc., the continuous innovation in this area has been a significant stimulation of the popularization of multimedia in modern life. For enhancement of coding performance, various new coding tools are adopted in the latest standards. Meanwhile, the use of these new technologies, along with the ever-increasing demand for emerging ultra-high-specification applications such as QFHD (Quad Full High Definition) and SHV (Super Hi-Vision), greatly challenges the design of video decoder chips, with the extensive requirements on both computation power and memory (DRAM) bandwidth. While the advancement of VLSI technology makes it possible to meet the requirement of computation power, the off-chip memory bandwidth is still critically limited by the number and physical design issues of I/O pins. With the current technologies, 4096x2160@60fps requires an average DRAM bandwidth of near 8GB/s, which cannot be handled even by the fastest DDR2 chips with 64-bit parallelism. Besides, DRAM bandwidth efficiency is also a dominant factor in determining the fabrication cost and power consumption of video decoder systems. In this dissertation, various optimization techniques classified into 3 categories are proposed to reduce the DRAM bandwidth of video decoder systems. By combining all the proposed techniques, around 90% saving of DRAM bandwidth can be achieved for high-throughput video decoders, in comparison with the Abstract-ii-state-of-the-art video decoder implementation. Besides, the architecture design of 2 implemented video decoder chips is also presented. This dissertation consists of the following 7 chapters. Chapter 1 [Introduction] introduces the background knowledge of video coding standards, and the DRAM bandwidth issue in video decoder design. Previous works related to this research and an overview of this dissertation, are also presented in this chapter. Chapter 2 [Data Reusing Techniques] presents the techniques for reusing the redundant data transferring between the DRAM and the decoder core. 1) A Pipelined 2-D Cache Architecture is proposed as a basic reference frame sharing component. Under the standard MB scanning order, it is capable of reusing almost all the overlapped reference regions inside MBs and between horizontally neighboring MBs. Therefore 60% DRAM bandwidth for reference frame read can be saved in comparison with the previous VBSMC scheme. 2) A Partial MB Reordering scheme is proposed to achieve an improved MB scanning order, so that most of the overlapped reference regions between vertically adjacent MBs can also be reused, which contributes …

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