Enhanced write performance of a 64 Mb phase-change random access memory

A 1.8 V 64 Mb phase-change RAM with improved write performance is fabricated in a 0.12 /spl mu/m CMOS technology. The improvement of RESET and SET distributions is based on cell current regulation and multiple step-down pulse generators. The read access time and SET-write time are 68 ns and 180 ns respectively.

[1]  Y.T. Kim,et al.  Full integration and reliability evaluation of phase-change RAM based on 0.24 /spl mu/m-CMOS technologies , 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

[2]  T. Lowrey,et al.  Ovonic unified memory - a high-performance nonvolatile memory technology for stand-alone memory and embedded applications , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[3]  R. Bez,et al.  An 8Mb demonstrator for high-density 1.8V Phase-Change Memories , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[4]  Byung-Gil Choi,et al.  Phase-Transition Random-Access Memory (PRAM) , 2004 .