Accurate data path models for fast RT-level power estimation

A methodology is presented for RT-level power estimation using cycle-accurate power models of common components, exploiting their functionality, regularity, and symmetry. The proposed methodology consists of three steps: creation of a set of look-up tables of primitive blocks, creation of a C power model for each data path component, estimation of power consumption of an RT-level circuit using a simulation engine that exploits the component's regular structure. The accuracy and the efficiency of the proposed models are compared using QuickSim as a real delay gate-level power estimator. Experimental results show that the proposed models exhibit <0.5% error in both average and cycle-by-cycle power, while they are about 50 times faster than QuickSim simulator of Mentor Graphics.