SoC Speed Binning Using Machine Learning and On-Chip Slack Sensors

Speed binning of system-on-chips (SoCs) using conventional <inline-formula> <tex-math notation="LaTeX">$F_{\mathrm {max}}$ </tex-math></inline-formula> test requires application of complex functional test patterns. Functional workload-based speed binning techniques incur high test-cost in terms of long test-time and complexity in functional test generation, and require high-end automatic test equipment. In this paper, we propose a novel speed binning flow that uses path timing slacks, extracted with robust digital embedded sensor IPs, of selected critical/near-critical paths. We apply machine learning techniques to model a predictor considering the extracted slacks and the <inline-formula> <tex-math notation="LaTeX">$F_{\mathrm {max}}$ </tex-math></inline-formula> values from a set of randomly tested die during wafer sort. The trained predictor is used to obtain the <inline-formula> <tex-math notation="LaTeX">$F_{\mathrm {max}}$ </tex-math></inline-formula> for the remaining chips. The proposed flow has been demonstrated in an SoC benchmark circuit at 28 nm technology. For sufficient number of training samples, <inline-formula> <tex-math notation="LaTeX">$F_{\mathrm {max}}$ </tex-math></inline-formula> is correctly predicted for 99% of the prediction samples.

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