Design and characteristics of a lightly doped drain (LDD) device fabricated with self-aligned titanium disilicide

An As-P double-diffused lightly doped drain (LDD) device has been designed and fabricated with a self-aligned titanium disilicide process. The device design was aided by using an analytical one-dimensional model, and analytic results agree well with experimental data on the avalanche breakdown voltage gain and the ratio of substrate current to source current. Threshold voltage and subthreshold characteristics of this device do not deviate from those of a conventional device without LDD and silicide. The drain avalanche breakdown voltage of the LDD device is higher by 2.5 V over the conventional device. Transconductance degradation was observed for the LDD devices due to the inherently high source-drain series resistance of the LDD structure. Substrate current is reduced and hot-electron reliability is greatly improved. The titanium disilicide process effectively reduces the sheet resistances of the source-drain diffusion and the polysilicon gate to 3 Ω/sq compared with 150 Ω/sq of the unsilicided counterparts. It is also found that larger polysilicon grain size increases the sheet resistance of the silicide gate due to discontinuous titanium disilicide formation on top of polysilicon.

[1]  T. Shibata,et al.  An Optimally Designed Process for Submicrometer MOSFET's , 1982, IEEE Journal of Solid-State Circuits.

[2]  Y. Nakagome,et al.  An As-P(n+-n-)double diffused drain MOSFET for VLSI's , 1983, IEEE Transactions on Electron Devices.

[3]  S. Morimoto,et al.  High-speed latchup-free 0.5-µm-channel CMOS using self-aligned TiSi2and deep-trench isolation technologies , 1983, 1983 International Electron Devices Meeting.

[4]  F. Hsu,et al.  Structure-enhanced MOSFET degradation due to hot-electron injection , 1984, IEEE Electron Device Letters.

[5]  N. G. Constantine.  Hot electron effects in MOSFET's , 1975 .

[6]  F. d'Heurle,et al.  Cross‐sectional transmission electron microscopy investigation of Ti/Si reaction on phosphorus‐doped polycrystalline silicon gate , 1986 .

[7]  Y. Matsumoto,et al.  An optimized and reliable LDD structure for 1-µm NMOSFET based on substrate current analysis , 1985, IEEE Transactions on Electron Devices.

[8]  J. Moll,et al.  Breakdown mechanism in short-channel MOS transistors , 1978, 1978 International Electron Devices Meeting.

[9]  E. M. Buturla,et al.  Steady-state analysis of field effect transistors via the finite element method , 1975 .

[10]  T. Shibata,et al.  An optimally designed process for submicrometer MOSFET's , 1982 .

[11]  S. Ogura,et al.  Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor , 1980 .

[12]  S. Murarka,et al.  Refractory silicides of titanium and tantalum for low-resistivity gates and interconnects , 1980, IEEE Transactions on Electron Devices.

[13]  Chenming Hu,et al.  An analytical breakdown model for short-channel MOSFET's , 1982, IEEE Transactions on Electron Devices.

[14]  A.K. Sinha,et al.  Refractory Silicides of Titanium and Tantalum for Low-Resistivity Gates and Interconnects , 1980, IEEE Journal of Solid-State Circuits.

[15]  Chenming Hu.  Hot-electron effects in MOSFETs , 1983, 1983 International Electron Devices Meeting.

[16]  C. Duvvury,et al.  Series resistance modeling for optimum design of LDD transistors , 1983, 1983 International Electron Devices Meeting.

[17]  K. Steinhubl.  Design of Ion-Implanted MOSFET'S with Very Small Physical Dimensions , 1974 .

[18]  L. Ephrath.  Selective Etching of Silicon Dioxide Using Reactive Ion Etching with CF 4 ‐ H 2 , 1979 .

[19]  P.E. Cottrell,et al.  Hot-electron emission in N-channel IGFET's , 1979, IEEE Transactions on Electron Devices.

[20]  J.Y.C. Sun,et al.  IIIB-1 degradation of 77-K MOSFET characteristics due to channel hot electrons , 1984, IEEE Transactions on Electron Devices.

[21]  W.W. Walker,et al.  Fabrication of high-performance LDDFET's with Oxide sidewall-spacer technology , 1982, IEEE Transactions on Electron Devices.

[22]  H. Hara,et al.  A New Instability in MOS Transistor Caused by Hot Electron and Hole Injection from Drain Avalanche Plasma into Gate Oxide , 1970 .

[23]  D. L. Critchlow,et al.  Fabrication of high-performance LDDFET's with Oxide sidewall-spacer technology , 1982 .

[24]  W.W. Walker,et al.  Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor , 1980, IEEE Transactions on Electron Devices.