Modeling transistor level masking of soft errors in combinational circuits
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[1] Abhijit Chatterjee,et al. Design of adaptive nanometer digital systems for effective control of soft error tolerance , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).
[2] Diana Marculescu,et al. MARS-C: modeling and reduction of soft errors in combinational circuits , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[3] Robert C. Aitken,et al. Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS , 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.
[4] R.C. Baumann,et al. Radiation-induced soft errors in advanced semiconductor technologies , 2005, IEEE Transactions on Device and Materials Reliability.
[5] Charles H.-P. Wen,et al. CASSER: A Closed-Form Analysis Framework for Statistical Soft Error Rate , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[6] Abhijit Chatterjee,et al. Soft-error tolerance analysis and optimization of nanometer circuits , 2005, Design, Automation and Test in Europe.
[7] Lloyd W. Massengill,et al. Charge deposition modeling of thermal neutron products in fast submicron MOS devices , 1999 .
[8] Shuming Chen,et al. Calculating the Soft Error Vulnerabilities of Combinational Circuits by Re-Considering the Sensitive Area , 2014, IEEE Transactions on Nuclear Science.
[9] Michele Favalli,et al. Fault simulation of unconventional faults in CMOS circuits , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[10] Bin Zhang,et al. FASER: fast analysis of soft error susceptibility for cell-based designs , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).