论文信息 - Implementation of a phase-locked loop clock recovery module for 40 Gb/s optical receivers

Implementation of a phase-locked loop clock recovery module for 40 Gb/s optical receivers

A low-cost, high-performance clock recovery (CR) module using a phase-locked loop (PLL) for 40 Gb/s optical receivers have been successfully designed and implemented. The recovered 40 GHz clock is synchronized with a stable 10 GHz VC-DRO. The timing jitter of the implemented PLL clock recovery module is significantly reduced as compared with the conventional open-loop type clock recovery module with a DR filter. The measured RMS jitter with the phase-locked CR module is about 250 fs. In addition, the CR module has been operated error-free during a 30-minute BER test with 40 Gb/s optical transceivers.

Kang Wook Kim | Chan Ho Park | Dong Sik Woo | Sang Kyu Lim | Tae Gyu Kim

[1] Jae Ho Song Song,et al. Design and Characterization of a 10 Gb/s Clock and Data Recovery Circuit Implemented with Phase-Locked Loop , 1999 .

[2] Kang Wook Kim,et al. A new design procedure of tapped coupled-line filters , 2004, IEEE Antennas and Propagation Society Symposium, 2004..

[3] T. Otsuji,et al. A novel clock recovery circuit for fully monolithic integration , 1999, 1999 IEEE MTT-S International Microwave Symposium Digest (Cat. No.99CH36282).

[4] Matjaz Vidmar,et al. 80 Gbit/s optical clock recovery with automatic lock acquisition using electrical phase-locked loop , 2003 .

[5] Y. Imai,et al. Design and performance of clock recovery GaAs ICs for high-speed optical communication systems , 1993 .

[6] G. Hanke,et al. Clock recovery circuits up to 20 Gbit/s for optical transmission systems , 1994, 1994 IEEE MTT-S International Microwave Symposium Digest (Cat. No.94CH3389-4).