Improving Signature Behavior by Irrevocability in Transactional Memory Systems

Signatures have been proposed in Hardware Transactional Memory (HTM) to represent read and write sets of transactions and decouple transaction conflict detection from private caches. Generally, signatures are implemented as Bloom filters that allow unbounded read/write sets to be summarized in bounded hardware, at the cost of address aliasing that causes false conflict detection. Such conflicts rises exponentially as signature fills so they can lead a parallel program to perform worse than its sequential counterpart (we say that signature saturates). In this work, irrevocability is proposed to address the signature saturation problem. When a transaction is near to saturate its signature, the transaction enters an irrevocable state that prevents it from being aborted. Then, such a transaction keeps running while the others are either stalled or allowed to run concurrently. Two variants of irrevocability are analyzed in this paper. Experimental evaluation on an HTM simulator shows the benefits in performance and power consumption of the proposed irrevocability mechanisms.

[1]  Michael Gschwind,et al.  The IBM Blue Gene/Q Compute Chip , 2012, IEEE Micro.

[2]  Maurice Herlihy,et al.  Virtualizing transactional memory , 2005, 32nd International Symposium on Computer Architecture (ISCA'05).

[3]  Emilio L. Zapata,et al.  Hardware Signature Designs to Deal with Asymmetry in Transactional Data Sets , 2013, IEEE Transactions on Parallel and Distributed Systems.

[4]  Burton H. Bloom,et al.  Space/time trade-offs in hash coding with allowable errors , 1970, CACM.

[5]  Andrew B. Kahng,et al.  ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[6]  Kunle Olukotun,et al.  STAMP: Stanford Transactional Applications for Multi-Processing , 2008, 2008 IEEE International Symposium on Workload Characterization.

[7]  Bradley C. Kuszmaul,et al.  Unbounded Transactional Memory , 2005, HPCA.

[8]  Adam Welc,et al.  Irrevocable transactions and their applications , 2008, SPAA '08.

[9]  Milo M. K. Martin,et al.  Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset , 2005, CARN.

[10]  Oscar Plata,et al.  LS-Sig: Locality-Sensitive Signatures for Transactional Memory , 2013, IEEE Transactions on Computers.

[11]  Maged M. Michael,et al.  Evaluation of Blue Gene/Q hardware support for transactional memories , 2012, 2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT).

[12]  R. I. Bahar,et al.  Energy-Aware Microprocessor Synchronization : Transactional Memory vs . Locks , 2006 .

[13]  Mike Dai Wang Exploring the Performance and Programmability Design Space of Hardware Transactional Memory , 2014 .

[14]  Milo M. K. Martin,et al.  Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol , 2002, IEEE Trans. Parallel Distributed Syst..

[15]  Daniel Sánchez,et al.  Implementing Signatures for Transactional Memory , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).

[16]  Sally A. McKee,et al.  Performance and Energy Analysis of the Restricted Transactional Memory Implementation on Haswell , 2014, 2014 IEEE 28th International Parallel and Distributed Processing Symposium.

[17]  Jeffrey T. Draper,et al.  Unified Signatures for Improving Performance in Transactional Memory , 2011, 2011 IEEE International Parallel & Distributed Processing Symposium.

[18]  Michael L. Scott,et al.  Flexible Decoupled Transactional Memory Support , 2008, 2008 International Symposium on Computer Architecture.

[19]  Niraj K. Jha,et al.  GARNET: A detailed on-chip network model inside a full-system simulator , 2009, 2009 IEEE International Symposium on Performance Analysis of Systems and Software.

[20]  David A. Wood,et al.  LogTM: log-based transactional memory , 2006, The Twelfth International Symposium on High-Performance Computer Architecture, 2006..

[21]  Fredrik Larsson,et al.  Simics: A Full System Simulation Platform , 2002, Computer.

[22]  David A. Wood,et al.  LogTM-SE: Decoupling Hardware Transactional Memory from Caches , 2007, 2007 IEEE 13th International Symposium on High Performance Computer Architecture.

[23]  Maurice Herlihy,et al.  Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems , 2010, J. Parallel Distributed Comput..

[24]  James R. Larus,et al.  Transactional Memory , 2006, Transactional Memory.

[25]  Maurice Herlihy,et al.  Transactional Memory: Architectural Support For Lock-free Data Structures , 1993, Proceedings of the 20th Annual International Symposium on Computer Architecture.

[26]  Josep Torrellas,et al.  Bulk Disambiguation of Speculative Threads in Multiprocessors , 2006, 33rd International Symposium on Computer Architecture (ISCA'06).

[27]  Milo M. K. Martin,et al.  Unrestricted Transactional Memory: Supporting I/O and System Calls Within Transactions , 2006 .