Adaptive combinational logic circuits based on intrinsic Evolvable Hardware

Evolvable Hardware(EHW) has been proposed as a promising technology for adaptive systems in last few years. However, in practical applications, evolutionary algorithms(EAs) often need numerous generations to search a new solution. In general, a mistaken system is damaged if it cannot restore in time, so the inefficiency problem has become an obstacle of developing adaptive and evolvable hardware. This paper analyzes how those three factors as genotype, algorithm, and methodology affect the efficiency of the EAs, as well as to what extent of their influence respectively, then proposes parallel and recursive decomposition (PRD) as a new decomposition strategy to accelerate the adaptation process from methodology perspective. Finally, some adaptive combination logical circuits are implemented on Xilinx Virtex-II Pro (XC2VP20) FPGA. The results demonstrate that PRD has more improvement on adaptation speed than some previous strategies.

[1]  Mehrdad Salami,et al.  Evolvable hardware at function level , 1997, Proceedings of 1997 IEEE International Conference on Evolutionary Computation (ICEC '97).

[2]  Julian Francis Miller,et al.  A multi-chromosome approach to standard and embedded cartesian genetic programming , 2006, GECCO.

[3]  Jim Tørresen,et al.  A Divide-and-Conquer Approach to Evolvable Hardware , 1998, ICES.

[4]  Tatiana Kalganova,et al.  Bidirectional incremental evolution in extrinsic evolvable hardware , 2000, Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware.

[5]  Marco Platzner,et al.  Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution , 2007, ARCS.

[6]  Adrian Stoica,et al.  Evolvable hardware solutions for extreme temperature electronics , 2001, Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001.

[7]  Jonathan Timmis,et al.  Evolvable Hardware, a Fundamental Technology for Homeostasis , 2007, 2007 IEEE Workshop on Evolvable and Adaptive Hardware (WEAH2007).

[8]  Julian Francis Miller,et al.  Cartesian genetic programming , 2000, GECCO '10.

[9]  Adrian Stoica,et al.  Adaptive and Evolvable Hardware - A Multifaceted Analysis , 2007, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007).

[10]  Pauline C. Haddow,et al.  From here to there : future robust EHW technologies for large digital designs , 2001, Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001.

[11]  E. Stomeo,et al.  Generalized Disjunction Decomposition for Evolvable Hardware , 2006, IEEE Transactions on Systems, Man, and Cybernetics, Part B (Cybernetics).

[12]  Vishal Sahni,et al.  An embryonic approach to reliable digital instrumentation based on evolvable hardware , 2003, IEEE Trans. Instrum. Meas..

[13]  Gunnar Tufte,et al.  An evolvable hardware FPGA for adaptive hardware , 2000, Proceedings of the 2000 Congress on Evolutionary Computation. CEC00 (Cat. No.00TH8512).

[14]  John C. Gallagher,et al.  On Learning to Trust the Unexpected: Toward a Systematic Apologetic for Evolvable Hardware , 2007, 2007 IEEE Workshop on Evolvable and Adaptive Hardware (WEAH2007).

[15]  Tatiana Kalganova,et al.  On evolution of relatively large combinational logic circuits , 2005, 2005 NASA/DoD Conference on Evolvable Hardware (EH'05).

[16]  Tatiana Kalganova.  An Extrinsic Function-Level Evolvable Hardware Approach , 2000, EuroGP.

[17]  Xin Yao,et al.  Promises and challenges of evolvable hardware , 1996, IEEE Trans. Syst. Man Cybern. Part C.

[18]  Joaquin Sitte,et al.  Gate-level Morphogenetic Evolvable Hardware for Scalability and Adaptation on FPGAs , 2006, First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06).

[19]  Gunnar Tufte,et al.  Bridging the genotype-phenotype mapping for digital FPGAs , 2001, Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001.